Description of the Related Art
A phase change memory device, such as, a phase change random access memory (PRAM), is an example of a related art nonvolatile memory device. A related art PRAM records and reads bit data using resistance characteristics of a phase change layer. These resistance characteristics are varied according to a phase of the phase change layer. Other types of related art nonvolatile memory devices are flash memories, ferroelectric random access memories (FRAM), magnetic random access memories (MRAM), and the like. A structural difference between PRAMs and other related art nonvolatile memory devices is the storage node.
FIG. 1 shows a storage node of an example related art PRAM. As shown, the related art storage node includes a lower electrode 10, a lower electrode contact layer 12, a phase change layer 14 and an upper electrode 16 as illustrated in FIG. 1. In example operation, if a reset pulse current reset is applied to the storage node for a first time period (e.g., a relatively short time period), a portion of the phase change layer 14 contacting the lower electrode contact layer 12 changes to an amorphous region 18. In this example, the resistance of the amorphous region 18 is greater than the resistance of the phase change layer 14 in a crystalline state.
In related art PRAMs having a storage node structured as illustrated in FIG. 1, a write current applied to the PRAM to form the amorphous region in the phase change layer 14 may exceed an allowable current value for a transistor of the PRAM.
Moreover, integration of related art PRAMs may be increased by reducing transistor sizes and/or storage node size. However, if the size of the transistor is reduced, a maximum current allowable in the transistor may be reduced. As a result, unless the reset current applied during a write operation of the PRAM is reduced to lower than a maximum current allowable in the transistor, increasing integration density of PRAMs may be more difficult.
According to the related art, a reset current may be reduced by reducing a width of the lower electrode contact layer in the storage node, oxidizing the lower electrode contact layer or using a higher resistance TiAlN layer for the lower electrode contact layer. However, in related art methods, production yield and/or reliability of related art PRAMs may deteriorate because a set resistance may be increased.